----------------------------------------------------------------------------------
-- Company: Ensimag
-- Engineer: Muller,VIARDOT
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity processeur is
  Port (
    CLK             : in  STD_LOGIC;
    RESET    : in  STD_LOGIC;
    ADPROG   : out  STD_LOGIC_VECTOR (15 downto 0);
    DPROG    : in  STD_LOGIC_VECTOR (15 downto 0);

    ADDATA   : out  STD_LOGIC_VECTOR (15 downto 0);
    DDATAIN  : in  STD_LOGIC_VECTOR (15 downto 0);
    DDATAOUT : out  STD_LOGIC_VECTOR (15 downto 0);
    WE       : out  STD_LOGIC;
    CE       : out  STD_LOGIC;
    OE       : out  STD_LOGIC;
    
    PIN      : in  STD_LOGIC_VECTOR (3 downto 0);
    POUT     : out  STD_LOGIC_VECTOR (7 downto 0)
    );
end Processeur;

architecture structural of processeur is
  component PC
    Port (
      CLK      : in  STD_LOGIC;
      RESET    : in  STD_LOGIC;
      RST      : out  STD_LOGIC;

      ERd      : out  STD_LOGIC;
      SelRa    : out  std_logic_vector(2 downto 0);			  
      SelRb    : out  std_logic_vector(2 downto 0);			  
      SelRd    : out  std_logic_vector(2 downto 0);			  
      SelRin   : out  std_logic_vector(1 downto 0);			  			  
      EOUT     : out  STD_LOGIC;			  

      CLRPC    : out  STD_LOGIC;
      EPC      : out  STD_LOGIC;
      LDPC     : out  STD_LOGIC;
      SelPC    : out  STD_LOGIC;
      
      selA     : out  STD_LOGIC;
      selB     : out  STD_LOGIC;
      ImmB      : out STD_LOGIC_VECTOR(15 downto 0);
      
      op       : out std_logic_vector(5 downto 0);
      ECarry   : out STD_LOGIC;
      
      EIR      : out  STD_LOGIC;
      IR       : in STD_LOGIC_VECTOR(15 downto 0);
      
      selCond  : out  STD_LOGIC_VECTOR (2 downto 0);
      cond     : in STD_LOGIC;
      
      
      WE       : out  STD_LOGIC;
      CE       : out  STD_LOGIC;
      OE       : out  STD_LOGIC
      
      );
  end component;
  component PO
    Port (
      CLK      : in  STD_LOGIC;
      RST      : in  STD_LOGIC;
      

      SelRa    : in  std_logic_vector(2 downto 0);			  
      SelRb    : in  std_logic_vector(2 downto 0);			  
      SelRd    : in  std_logic_vector(2 downto 0);			  
      SelRin   : in  std_logic_vector(1 downto 0);			  			  
      ERd      : in  STD_LOGIC;
      EOUT     : in  STD_LOGIC;			  

      CLRPC    : in  STD_LOGIC;
      EPC      : in  STD_LOGIC;
      LDPC    : in  STD_LOGIC;
      SelPC    : in  STD_LOGIC;
      
      selA     : in  STD_LOGIC;
      selB     : in  STD_LOGIC;
      ImmB      : in STD_LOGIC_VECTOR(15 downto 0);
      
      op       : in std_logic_vector(5 downto 0);
      ECarry   : in STD_LOGIC;
      
      EIR      : in  STD_LOGIC;
      IR       : out STD_LOGIC_VECTOR(15 downto 0);

      selCond  : in  STD_LOGIC_VECTOR (2 downto 0);
      cond     : out STD_LOGIC;
      
      ADPROG   : out  STD_LOGIC_VECTOR (15 downto 0);
      DPROG    : in  STD_LOGIC_VECTOR (15 downto 0);
      
      ADDATA   : out  STD_LOGIC_VECTOR (15 downto 0);
      DDATAIN  : in  STD_LOGIC_VECTOR (15 downto 0);
      DDATAOUT : out  STD_LOGIC_VECTOR (15 downto 0);
      
      PIN      : in  STD_LOGIC_VECTOR (3 downto 0);
      POUT     : out  STD_LOGIC_VECTOR (7 downto 0)
      );
  end component;
  
  signal RST       :  STD_LOGIC;

  signal sERd       :  STD_LOGIC;
  signal SelRa     :  std_logic_vector(2 downto 0);			  
  signal SelRb     :  std_logic_vector(2 downto 0);			  
  signal SelRd     :  std_logic_vector(2 downto 0);			  
  signal SelRin    :  std_logic_vector(1 downto 0);			  			  
  signal EOUT      :  STD_LOGIC;			  

  signal CLRPC     :  STD_LOGIC;
  signal sEPC       :  STD_LOGIC;
  signal sLDPC     :  STD_LOGIC;
  signal SelPC     :  STD_LOGIC;
  
  signal selA      :  STD_LOGIC;
  signal selB      :  STD_LOGIC;
  signal ImmB       : STD_LOGIC_VECTOR(15 downto 0);
  
  signal op        : std_logic_vector(5 downto 0);
  signal ECarry    : STD_LOGIC;
  
  signal EIR       :  STD_LOGIC;
  signal sIR        : STD_LOGIC_VECTOR(15 downto 0);

  signal selCond   :  STD_LOGIC_VECTOR (2 downto 0);
  signal cond      : STD_LOGIC;

  
  
begin
  
  PCinst: PC
    port map (
      CLK     => CLK    ,
      RESET   => RESET  ,
      RST      => RST      ,

      
      SelRa   => SelRa  ,
      SelRb   => SelRb  ,
      SelRd   => SelRd  ,
      SelRin  => SelRin ,
      ERd     => sERd    ,
      EOUT    => EOUT   ,

      CLRPC   => CLRPC  ,
      EPC     => sEPC    ,
      LDPC    => sLDPC,
      SelPC   => SelPC  ,

      selA    => selA     ,
      selB    => selB     ,
      ImmB     => ImmB      ,

      op      => op,
      ECarry  => ECarry ,

      EIR     => EIR    ,
      IR      => sIR     ,

      selCond => selCond ,
      cond    => cond   ,

      WE      => WE     ,
      CE      => CE     ,
      OE     => OE     

      );
  POinst: PO
    port map(
      CLK      => CLK      ,
      RST      => RST      ,

      SelRa    => SelRa    ,
      SelRb    => SelRb    ,
      SelRd    => SelRd    ,
      SelRin   => SelRin   ,
      ERd      => sERd      ,
      EOUT     => EOUT     ,

      CLRPC    => CLRPC    ,
      EPC      => sEPC      ,
      LDPC    => sLDPC,
      SelPC    => SelPC    ,

      selA     => selA     ,
      selB     => selB     ,
      ImmB      => ImmB      ,

      op       => op,
      ECarry   => ECarry   ,

      EIR      => EIR      ,
      IR       => sIR       ,

      selCond  => selCond  ,
      cond     => cond     ,

      ADPROG   => ADPROG   ,
      DPROG    => DPROG    ,

      ADDATA   => ADDATA   ,
      DDATAIN  => DDATAIN  ,
      DDATAOUT => DDATAOUT ,

     
      PIN      => PIN      ,
      POUT     => POUT
      );

end structural;
